1. Field of Invention
The present invention relates to an integrated circuit (IC) process, and particularly to a method of forming a semiconductor device.
2. Description of Related Art
As the level of integration of a non-volatile memory is getting higher, the critical dimension of the same is getting smaller. Minimizing the critical dimension and increasing the level of integration have become the mainstream in the industry, and the key technology is in photolithography.
In the photolithography stage, reducing a pitch to less than 38 nm in the current state of technology is rather difficult even by immersion 193 nm (ArF) scanner combined with a self-aligned double patterning (SADP) process, unless a light source having a shorter wavelength (for example, by 13 nm EUV scanner) and a corresponding photoresist are used. However, it is very costly to replace existing machines entirely with new machines for this purpose. Thereafter, a double spacer forming technique such as a self-aligned quadruple patterning (SAQP) process is developed.
In the SADP or SAQP process, two spacers are provided beside each core pattern, and the spacers are usually formed with tilted sidewalls. In such case, the adjacent spacers are easily connected and merged in the subsequent patterning process. Accordingly, how to resolve the spacer merge issue and thereby improve the device performance has been drawn attention in the industry.